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Preliminary
EP9312 Product Overview
FEATURES
I 200MHz ARM920T Processor -- 16kbyte Instruction Cache -- 16kbyte Data Cache -- Windows CE enabled MMU I MaverickCrunch TM Math Engine -- Floating point, integer and signal processing instructions -- Optimized for digital music compression and decompression algorithms -- Hardware interlocks allow in-line coding I MaverickLock TM Security Features -- Incorporates boot ROM, laser fuses, and gate-level IP -- Multiple security vendors can co-exist in same system -- Exceeds SDMI requirements (Cont.)
Internet Audio Jukebox Processor with MaverickCrunchTM Audio Compression and MaverickLock TM Security
OVERVIEW
The EP9312 is an ARM920T based system on chip designed for use in audio jukebox applications where processor performance, signal processing capability, communications bandwidth, storage capabilities, and the user interface are properly balanced to provide up to 4 streams of compressed audio data (MP3, WMA, and other audio compression standards) through a home network.
(Cont.)
BLOCK DIAGRAM
Serial Audio Interface
Peripheral Bus
Clocks & Timers
USER INTERFACE
SERIAL PORTS
DMA w/ CRC (3) UARTs w/ IRDA
MaverickCrunch TM ARM920T
Interrupts & GPIO
MaverickLockTM
D-Cache 16KB
I-Cache 16KB
Bus Bridge
(3) USB Hosts
Boot ROM
MMU
Keypad & Touch Screen I/F Processor Bus
Ethernet MAC
EIDE I/F
SRAM & Flash I/F
Unified SDRAM I/F
Video/LCD Controller
MEMORY AND STORAGE (c)Copyright 2001 Cirrus Logic (All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
Jan'01 DS515PO3 1
EP9312 Internet Audio Jukebox Processor
Preliminary
FEATURES
(cont.)
I Integrated Peripheral Interfaces -- EIDE (up to 2 devices) -- 1/10/100Mbps Ethernet MAC -- Three 16550 compatible UARTs -- Three-port USB Host -- IRDA Interface -- 32-bit SDRAM Interface up to 4 banks -- 32/16-bit SRAM/FLASH/ROM -- EEPROM Interface
I Internal Peripherals -- Real-time Clock with software Trim -- Eight Direct Memory Access (DMA) Channels with Cyclic Redundancy Check (CRC) Generation -- Dual PLL controls all clock domains -- Watchdog Timer -- Interrupt Controller -- Four general purpose 16-bit timers -- 40-bit Debug Timer -- Boot ROM I Package -- 352 pin PBGA
(cont.) The ARM920T microprocessor core with separate 16Kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunchTM coprocessor enabling faster than real-time compression of audio CDs. The proprietary MaverickLockTM technology exceeds security requirements set forth by SDMI to protect music content. It may also be used to protect proprietary firmware, transactions, and other digital content. A high-performance 1/10/100Mbps Ethernet Media Access Controller (EMAC) is included along with
OVERVIEW
external interfaces to SPI and I2S audio, LCD, IDE storage peripherals, keypad, and touchscreen. A threeport USB host and three UARTs are included as well. The EP9213 is a high-performance, low-power RISCbased single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200MHz. The ARM core is operateS from a 2.5V supply, while the I/O operates at 3.3V with power between 350mW and 1000mW dependent on speed.
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Preliminary
Internet Audio Jukebox Processor
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with separate 16Kbyte instruction and data caches with an 8word line length. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. Key features include: * ARM (32-bit) and Thumb (16-bit compressed) instruction sets * 32-bit Advanced Micro-Controller Bus Architecture (AMBA) * 16Kbyte Instruction Cache with lockdown * 16Kbyte Data Cache (programmable writethrough or write-back) with lockdown * MMU for Microsoft (R) Windows (R) CE and other operating systems * Translation Look Aside Buffers with 64 Data and 64 Instruction Entries * Programmable Page Sizes of 64Kbyte, 4Kbyte, and 1Kbyte * Independent lockdown of TLB Entries
from several security vendors including Microsoft(R) and InterTrust(R) . It exceeds all the requirements set forth by SDMI and allows for protection of object code as well as content. Features include: * 256 bits of laser fuses for permanent IDs and passwords * Security boot firmware and private passwords are "invisible" except when the IC is "locked" * Each instantiation of the system software may be uniquely encoded and protected by using the private ID * Multiple security vendors can co-exist in the same system
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
The Maverick 9312 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal port is dedicated to the read-only LCD refresh engine, while the rest of the memory accesses are performed via the Advanced High Performance Bus (AHB). The memory controller supports both 16- and 32-bit devices and accommodates a 16-bit boot ROM concurrently with 32bit SDRAM memory. * 1-4 banks of 32-bit 66 or 100MHz SDRAM * One internal port dedicated to the LCD Refresh Engine (Read Only) * One internal port dedicated to the rest of the chip via the AHB * Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory * Either NAND or NOR FLASH memory supported
Table A. General Purpose Memory Interface Pin Assignments
MaverickCrunch TM Math Engine
The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiplyaccumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: * IEEE-754 single and double precision floating point * 32/64-bit integer * Add/multiply/compare * Integer MAC 32-bit input with 72-bit accumulate * Integer Shifts * Floating point to/from integer conversion * Sixteen 64-bit register files * Four 72-bit accumulators
Pin Mnemonic
SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:0]
I/O
O O O O O O O O I/O O
Pin Description
SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects 3-0 SDRAM RAS SDRAM CAS SDRAM Write Enable Chip Selects 7-0 Address Bus 25-0 Data Bus 31-00 SDRAM Output Enables / Data Masks
MaverickLockTM Security
MaverickLock security is a generalized architecture consisting of boot ROM, laser fuses, and proprietary circuitry for secure hardware initialization. In the context of this environment, the EP9312 supports multiple digital rights management content protection
DS515PO3
AD[25:0] DA[31:0] DQMn[3:0]
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Internet Audio Jukebox Processor
Preliminary
Table A. General Purpose Memory Interface Pin Assignments
Pin Mnemonic
WRn RDn WAITn
I/O
O O I
Pin Description
SRAM Write Strobe SRAM Read/OE Strobe Wait Input
* Hardware Blinking * 6-bit Contrast DAC
Table C. LCD Interface Pin Assignments
Pin Mnemonic
SPCLK
I/O
I/O O O O O O O
Pin Description
Pixel Clock Pixel Data Bus [17:0] Horizontal Synchronization/Line Pulse Vertical or Composite Synchronization / Frame Pulse Composite Blank Pulse Width Modulated Brightness Contrast DAC Output
IDE Interface
The IDE Interface provides an industry-standard connection to two AT Packet Interface (ATAPI) compliant devices. Each device may be controlled by any of the 8 DMA controllers. The IDE port will attach to a master and a slave device. The internal DMA controller performs all data transfers using the Multiword DMA and Ultra DMA modes. The interface supports the following operating modes: * PIO Mode 4 * Multiword DMA Mode 2 * Ultra DMA Mode 2
Table B. IDE Interface Pin Assignments
P[17:0) HSYNC/LP VCSYNC/FP BLANK BRIGHT CDACO
Ethernet Media Access Controller (EMAC)
The MAC subsystem is compliant with the ISO/TEC 8802-3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: * Supports 1/10/100Mbps transfer rates for home/small-business/large-business applications * Interfaces to an off-chip PHY through industry standard Media Independent Interface (MII) * May be configured entirely by the driver or through auto-negotiation
Table D. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
DD[15-0] IDEDA[2-0] IDECSn[0,1] DIORn IDORWn DMACKn
I/O
I/O O O O O O
Pin Description
IDE Data bus IDE Device address IDE Chip Select 0 and 1 IDE Read Strobe IDE Write Strobe IDE DMA acknowledge
LCD Interface
The LCD interface provides data and interface signals for a variety of display types. It features fully programmable video interface timing for non-interlaced flat panel or dual scan displays. Resolutions up to 1024x768 are supported from a unified SDRAM based frame buffer. A 6-bit DAC provides an analog DC voltage output for the LCD panel contrast control. LCD specific features include: * Provides timing and interface signals for digital LCD and TFT displays * Fully programmable for either non-interlaced or dual-scan color and grayscale flat panel displays * Dedicated data path to SDRAM controller for improved system performance * Pixel depths of 4-, 8-, 16-, or 18-bits per pixel or 256 levels of grayscale * Hardware Cursor up to 64 x 64 x 2 pixels * 256 x 18 Color Lookup Table
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Pin Mnemonic
MDC MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD
I/O
O I/O I I I I I/O O O O I I
Pin Description
Management Data Clock Management Data I/O Receive Clock Receive Data Receive Data Valid Receive Data Error Transmit Clock Transmit Data Transmit Enable Transmit Error Carrier Sense Collision Detect
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
DS515PO3
EP9312 Preliminary
Internet Audio Jukebox Processor
Touch Screen Interface with 12-bit Analogto-Digital Converter (ADC)
The touch screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog resistive touch screens. This controller only interrupts the processor when a meaningful change occurs. The touch screen hardware may be disabled and the switch matrix and ADC controlled directly if desired. Features include: * Supports 4-, 5-, 7-, or 8-wire analog resistive touch screens * Unused lines may be used for temperature sensing or other functions * Touch screen interrupt function is provided.
Table E. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments
Audio Interfaces (SPI and I2S)
Two SPI ports are independently configured as masters or slaves, supporting the Motorola (R) , National Semiconductor(R) , and Texas Instruments(R) signaling protocols. SPI port 0 may be configured as an Inter-IC Sound (I2 S) port. * Two SPI Ports * Alternative I 2 S Port
Table G. Audio Interfaces Pin Assignments
Pin Mnemonic
SCLK[0] SFRM[0] SSPRX(0) SSPTX(0) SCLK[1] SFRM[1] SPRX(1) SSPTX(1) ARSTn
I/O
O O I O O O I O O
Pin Description
SPI[0] Clock SPI[0] Frame Clock SPI[0] Input SPI[0] Output SPI[1] Clock SPI[1] Frame Clock SPI[1] Input SPI[1] Output -
Alternative Usage (I2 S)
SCLK LRCLK SDI SDO None None None None MCCLK
Pin Mnemonic
Xp,Xm Yp, Ym SXp, SXm SYp, SYm
I/O
O O I I
Pin Description
Touch screen ADC X Axis Touch screen ADC Y Axis Touch screen ADC X Axis Voltage Feedback Touch screen ADC Y Axis Voltage Feedback
64-Keypad Interface
The keypad circuitry scans an 8x8 array of 64 normally open, single pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general purpose I/O. * Provides scanning, debounce and decoding for a 64-key array * Scans an 8-row by 8-column matrix * Up to 2 keys may be decoded at once * An interrupt is generated when new stable key is determined * Also generates a 3-key reset interrupt
Table F. 64-Key Keypad Interface Pin Assignments
Triple Port USB Host
The USB host controller is configured for three root hub ports and features integrated transceivers for each port. The controller complies with the Open Host Controller Interface (OHCI) Specification for USB, Revision 1.1.
Table H. Triple Port USB Host Pin Assignments
Pin Mnemonic
USBp[2:0] USBm[2:0] USBVDD[1:0] USBGND[1:0]
I/O
I/O I/O NA NA
Pin Name - Description
USB Positive signals USB Negative Signals USB Power USB Ground
Pin Mnemonic
COL[7:0] ROW[7:0]
I/O
I O
Pin\ Description
Key Matrix Column Inputs Key Matrix Row Inputs
Alternative Usage
General Purpose I/O General Purpose I/O
DS515PO3
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Internet Audio Jukebox Processor
Preliminary
Universal Asynchronous Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two provide asynchronous (High-level Data Link Control) HDLC protocol support for full duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. A third IrDA(R) compatible UART is also supplied. * UART1 supports modem bit rates up to 115.2Kbps, supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and modem status change. * UART2 contains an IrDA encoder operating at either the slow (115Kbps) or fast (4Mbps) IR data rates * UART3 supports HDLC link layer protocol for transmission over synchronous networks
Table I. Universal Asynchronous Receiver / Transmitters Pin Assignments
vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible while maintaining RPS compatibility. Internal interrupts may be programmed as active high or active low level sensitive inputs. External interrupts may be programmed as active high level sensitive, active low level sensitive, rising edge triggered, falling edge triggered, or triggered from both. * Supports 56 interrupts from a variety of sources (such as UARTs, GPIO, and key matrix.) * Routes interrupt sources to either the ARM920T's IRQ or FIQ (Fast IRQ) inputs * Four dedicated off-chip interrupt lines operate as either edge triggered or level sensitive interrupts * Any of the 16 GPIO lines maybe configured to generate interrupts * Software supported priority mask for all FIQs and IRQs
Table J. Interrupt Controller Pin Assignment
Pin Mnemonic
INT[3:0]
Pin Name - Description
External Interrupt 3-0
Real-Time Clock with Software Trim
* Provides software controlled digital compensation of the 32.768KHz crystal oscillator * Accurate to +/- 5sec/month
Table K. Real-Time Clock with Pin Assignments
Pin Mnemonic
TXD[0] RXD[0] CTSn DSRn/DCDn DTRn RTSn EGPIO[0]/RI TXD[1]/SIROUT RXD[1]/SIRIN TXD[2] RXD[2] EGPIO[3]/TEN
I/O
O I I I O O I O I O I O
Pin Name - Description
UART1 Transmit UART1 Receive UART1 Clear To Send / Transmit Enable UART1 Data Set Ready / Data Carrier Detect UART1 Data Terminal Ready UART1 Ready To Send UART1 Ring Indicator UART2 Transmit / IrDA Output UART2 Receive / IrDA Input UART3 Transmit UART3 Receive UART3 Transmit Enable
Pin Mnemonic
RTCXTALI RTCXTALO RTCVDD RTCGND
Pin Name - Description
Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output Real-Time Clock Oscillator Power Real-Time Clock Oscillator Ground
Timers
* Watchdog Timer insures proper operation by requiring periodic attention to prevent a reset on time out * Four 16-bit timers operate as free running downcounters or as periodic timers for fixed interval interrupts and have a range of 0.03ms to 4.27seconds * 32-bit timer plus 6-bit prescale counter has a range of 0.03 s to 73.3hours * 40-bit debug timer plus 6-bit prescale counter has a range of 1.0 s to 12.7 days
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Interrupt Controller
The interrupt controller has 56 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments provided for assisting IRQ
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(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
EP9312 Preliminary
Internet Audio Jukebox Processor
PLL and Clocking
* Processor and Peripheral Clocks operate from a single 3.6864MHz crystal * Real-Time Clock operates from a 32.768 K H z crystal
Table L. PLL and Clocking Pin Assignments
Pin Mnemonic
XTALI XTALO PLLVDD PLLGND
Pin Name - Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
* Both LED Outputs * EEPROM Clock and Data * SLA [1:0] * 6 pins may alternatively be used as inputs only: * CTSn, DSRn/DCDn * 4 Interrupt Lines * 2 pins may alternatively be used as outputs only: * RTSn * ARSTn
Table O. General Purpose Input/Output Pin Assignment
Pin Mnemonic
EGPIO[15:0]
Pin Name - Description
Expanded General Purpose Input / Output Pins w/ Interrupts
Two-Wire Interface With EEPROM Support
* Communication and control for EEPROM devices. * EEPROM Controller may download device configuration information upon chip reset
Table M. Two-Wire Port with EEPROM Support Pin Assignments
Reset and Power Management
* The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn * Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power * The processor clock is dynamically adjustable from 0 to 200MHz
Table P. Reset and Power Management Pin Assignments
Pin Mnemonic
EECLK EEDATA SLA[1:0]
Pin Name - Description
EEPROM / Two-Wire Interface Clock EEPROM / Two-Wire Interface Data External Power Switch Control
Alternative Usage
General Purpose I/O General Purpose I/O General Purpose I/O
Pin Mnemonic
PRSTn RSTOn
Pin Name - Description
Power On Reset User Reset In/Out - Open Drain - Preserves Real Time Clock value
Dual LED Drivers
* Two pins assigned specifically to drive LEDs
Table N. Dual LED Pin Assignments
Hardware Debug Interface
* JTAG - Allows use of ARM's Multi-ICE or other in-circuit emulators
Table Q. Hardware Debug Interface
Pin Mnemonic
GRLED REDLED
Pin Name - Description
Green LED Red LED
Alternative Usage
General Purpose I/O General Purpose I/O
Pin Mnemonic
TCK TDI TDO
Pin Name - Description
JTAG Clock JTAG Data In JTAG Data Out JTAG Test Mode Select
General Purpose Input/Output (GPIO)
* 16 EGPIO pins may individually be used as an output, an input, or an interrupt input * 23 pins may alternatively be used as input, output, or open-drain pins but do not support interrupts: * Key Matrix ROW[7:0], COL[7:0] * Ethernet MDIO
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TMS
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Internet Audio Jukebox Processor
Preliminary
8-Channel DMA Controller with Four Hardware CRC Generators
The DMA module contains 8 separate DMA channels, Four Linear Feedback Shift Registers (LFSR), an 8-way Arbiter, a shared AHB bus master macrocell, a shared AHB register slave macrocell. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests from system resources such as UARTS. Each DMA channel can used independently or dedicated to any request signal. Each of the four LFSRs can also be dedicated to generate CRCs for their respective DMA channel or initialized by any AHB bus master as a separate entity. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or
stay at the same value. All DMA addresses are physical, not virtual addresses. * 8 DMA Controllers may each be used independently or dedicated to a requestor * CRC Generators may be hardware connected to DMA Channels or used independently * There are four CRC algorithms available: * CRC-16 * CRC-16 Reverse * CRC-CCITT, or CRC-CCITT Reverse * Programmable divisor polynomial allows customized CRC algorithms
Internal Boot ROM
* The Internal 16Kbyte ROM allows booting from FLASH memory, ROM or UART.
Absolute Maximum Ratings
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Power Supplies
Symbol
RVDD RTC_VDD CVDD PLL_VDD ADC_VDD DAC_VDD USB_VDD
Min
-0.3
Max
4.6 4.6 4.6 4.6 4.6 4.6 4.6 2 10 50 Vdd+ 0.3 125 150
Unit
V V V V V V V W mA mA V
Total Power Dissipation (Note1) Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage (Note2) Ambient temperature (power applied) (Note3) Storage temperature
-55 -65
C C
Note:
1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at recommended maximum values. 3. At ambient temperatures above 70 C, total power dissipation must be limited to less than TBD Watts.
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
DS515PO3
EP9312 Preliminary
Internet Audio Jukebox Processor
Recommended Operating Conditions
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter
Power Supplies (Note4)
Symbol
RVDD RTC_VDD CVDD PLL_VDD ADC_VDD DAC_VDD USB_VDD TA
Min
TBD TBD TBD TBD TBD TBD TBD 0
Typ
3.3 3.3 2.5 2.5 3.3 3.3 3.3 25
Max
TBD TBD TBD TBD TBD TBD TBD 70
Unit
V V V V V V V C
Operating Ambient Temperature
Note:
4. Minimum voltage on RTC_VDD is the level guaranteed to continue real time clock operation on battery power.
DC Characteristics
(TA = 0 to 70 C; CVDD = PLL_VDD= 2.5; RTC_VDD = RVDD = 3.3V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter
High level output voltage Low level output voltage High level input voltage Low level input voltage High level leakage current Low level leakage current Vin = 3.3 V Vin = 0 Iout = -5 mA Iout = 5 mA (Note6) (Note6) (Note6) (Note6) (Note5)
Symbol
Voh V ol V ih V il Iih Iil
Min
0.9xVdd 0.65xVdd -0.3 -
Max
0.1xVdd Vdd+0.3 0.35xVdd 10 -10
Unit
V V V V A A
Parameter Power Supply Pins (Outputs Unloaded)
Power Supply Current: RTC_VDD CVDD/PLL_VDD Total RVDD
Min
-
Typ
TBD 200 20 TBD
Max
TBD TBD TBD -
Unit
uA mA mA mA
Low-Power Mode Supply Current
Note:
5. For open drain pins, high level output voltage is dependent on external pull-up used and number of attached gates. 6. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation. If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor.
DS515PO3
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Internet Audio Jukebox Processor
Preliminary
Optional Silicon DAA (Soft Modem) Serial Audio Interface IS Audio CODECs
2
EP9312
Peripheral Bus APB AHB/ Processor Bus APB Bridge AHB Ethernet MAC
CS8952 Ethernet PHY
Home Network PHY DMA & CRC Generators 3 Port USB Host Optional USB Printer Portable Music Player Optional USB Keyboard/ Mouse
Clocks and Timers
MaverickCrunch Math Engine
TM
ARM920T
D-Cache 16KB Optional IR Based Keyboard or Remote Control UARTs (3) with IRDA I-Cache 16KB EIDE Interface
MMU
Static Memory Interface Boot ROM Interrupts and GPIO Unified SDRAM Interface
TM
EEPROM, FLASH, SRAM
Optional Parallel Printer Port
SDRAM
MaverickLock Security Front Panel Keypad Touch screen & Keypad Interface
LCD I/F
LCD Panel w/ Touch screen
Figure 1. Audio Jukebox Block Diagram
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(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
DS515PO3
EP9312 Preliminary
Internet Audio Jukebox Processor
352 Pin BGA Package Outline
O 0.30 S C A B O 0.10 S C
Ob 3 E3 E2 E
DETAIL B
D3 D2 D
(Top View)
B
A
2
-CA1
-A-
e
ddd C c E1
-BB D1
O A' A2
DETAIL A'
(Bottom View)
Figure 2. 352 Pin PBGA Pin Diagram
DS515PO3
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
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EP9312 Internet Audio Jukebox Processor
Preliminary
Table R. 352 Pin Diagram Dimensions
Symbol MIN
A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e ddd 2.20
dimension in mm NOM
2.30 0.60 1.17 0.75 0.56 27.00 24.13 24.00 18.00 27.00 24.13 24.00 18.00 1.27 ------30 TYP
dimension in inches MAX
2.50
MIN
0.087
NOM
0.092 0.024 0.046 0.030 0.022 1.063 0.950 0.945 0.709 1.063 0.950 0.945 0.709 0.050 ------30 TYP
MAX
0.098
---
1.12
---
1.22 ------0.61 27.20 ------24.20 18.05 27.20 ------24.20 18.05 ------0.15
---
0.044 ------0.020 1.055 ------0.937 0.707 1.055 ------0.937 0.707 -------------
---
0.048 ------0.024 1.071 ------0.953 0.711 1.071 ------0.953 0.711 ------0.006
---
0.51 26.80 ------23.80 17.95 26.80 ------23.80 17.95 -------------
Note:
1. CONTROLLING DIMENSION: MILLIMETER. 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25 mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. REFERENCE DOCUMENT: JEDEC MO-151, BAL-2
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(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
DS515PO3
EP9312 Preliminary
Internet Audio Jukebox Processor
352 Pin BGA Pinout (Top View)
1 A RDn
2 AD24 CSn6 DD12 CSn5 CGND DA28 DA24
3 AD20 AD23 DD11 DD14 CSn2 DA29 DA25
4 DD9 AD19 AD21 AD25 CSn3 DA30 nc DTRn
5 DD6 DD8 AD18 AD22 DSRn CSn1 CVDD DA27
6 AD17 DD4 DD7 DD10 RVDD RVDD RVDD
7 CGND AD16 DD3 DD5 RVDD RVDD
8 AD13 AD14 AD15 CVDD DD2
9 AD8 AD9 AD10 AD11 AD12
10 AD4 AD5 AD6 AD7 nc
11 AD3 AD1 AD0 DA19 AD2
12 DA23 DA22 DA21 DA18 CGND
13 DA20 DA17 DA16 DA11 DA8
14 DA15 CVDD DA12 DA6 RVDD RVDD
15 DA14 DA13 DA7 EGPIO 13 RVDD RVDD RVDD
16 DA10 DA9 EGPIO 12 DA4 DD0 RVDDRTC ASDI ARSTn EGPIO 2 COL7 nc RXD2
17
18
19 DA3 DA1 GNDRTC
20 DA2 DA0 A B
EGPIO10 EGPIO 14 EGPIO EGPIO11 15 DA5 DD1 RTCXTA LI ASDI2 DIORn EGPIO5 COL6 COL2 ROW4 TXD1 RTSn SLA0 WAITn
B CSn7 C DD13 D CSn4 E DA31 F DA26
RSTO C n
RTCXT PRSTn IORDY D ALO CSn0 DIOWn DMAC EGPIO E Kn 0 EGPIO EGPIO F 1 4
G WRn H
EGPIO EGPIO EGPIO G 3 6 7 EGPIO EGPIO CVDD H 8 9 CGND COL1 ROW5 ROW1 RXD1 INT3 COL5 COL3 ROW6 ROW2 TXD2 RXD0 INT2 CGND COL4 COL0 J K
SDCSn SDCSn SDCLK 1 2 EN CASn RASn
RGND RGND RGND RGND RGND RVDD RVDD RVDD P8 IDECS 0n RVDD P2 CVDD RVDD VS2 VS1 RGND
RGND RGND RGND RGND RGND RGND
RGND RGND RGND RGND RGND RGND
RGND RGND RGND RGND RGND RGND
RGND RGND RGND RGND RGND RGND
RGND RGND RGND RGND RGND RGND RVDD RVDD RVDD RVDD Yp SSPT X1 SSPR X1
J DQMn3
SDCSn0 SDCLK SDCSn 3 MDC
K DQMn2 DQMn0 SDWEn DQMn1 MIIRXD MIIRXD L RXCLK 2 3 M CGND MDIO
ROW7 L ROW3 M ROW0 N TXD0 CTSn P R
MIIRXD MIIRXD RXDVA RXERR 0 1 L CVDD BRIGHT P15 RVDDPLL SPCLK P6 P3 P1 TXERR P16 P10 GNDPLL P7 P0 IDECS 1n IDEDA 0
N TXCLK MIITXD MIITXD 3 2 MIITXD MIITXD P 1 0 R T U V CRS DD15 P17 P12 CLD BLANK P13 TXEN nc P14 P11
SLA1 RVDDUSB
RVDD USBm1 ABITCLK GRLED nc Xm Xp CGND CVDD GNDDAC sYp sXm sXp Ym USBp1 USBm2 RVDDADC GNDADC sYm ASDO
MCADE MCRDn Nn MCBVD MCWR 2 n MCDAE IOWRn Nn IORDn
nc TDI TCK MCRES ETn WP
TACK TEST0
SCLK1 INT1
CVDD T
USBp0 ASYNC RDLE U D USBp2 CDAC O nc nc V W Y
XTALO HSYNC V_CSY NC P5 nc P4
IDEDA READY MCD2 1 CGND IDEDA 2
TEST1 EEDAT TMS TDO
W XTALI Y P9
MCWAI MCBV MCREG Tn D1 n MCD1 MCDI R
SFRM EECLK 1 TREQA INT0
GNDUSBm0 USB GNDUSB
MCEHn MCELn
RVDD- RVDDDAC USB
DS515PO3
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
13
EP9312 Internet Audio Jukebox Processor
Preliminary
The following BGA ball assignment table is sorted in order of ball.
Ball
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
Signal
RDn AD[24] AD[20] DD[9] DD[6] AD[17] CGND AD[13] AD[8] AD[4] AD[3] DA[23] DA[20] DA[15] DA[14] DA[10] EGPIO[10] EGPIO[14] DA[3] DA[2] CSn[7] CSn[6] AD[23] AD[19] DD[8] DD[4] AD[16] AD[14] AD[9] AD[5] AD[1] DA[22] DA[17] CVDD DA[13] DA[9] EGPIO[11] EGPIO[15] DA[1] DA[0] DD[13] DD[12] DD[11] AD[21] AD[18] DD[7] DD[3] AD[15] AD[10] AD[6]
Ball
E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F6 F7 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G15 G16 G17 G18 G19 G20 H1 H2 H3 H4 H5 H8 H9 H10 H11 H12 H13 H16
Signal
AD[12] **NC** AD[2] CGND DA[8] RVDD RVDD DD[0] RTCXTALI CSn[0] DMACKn EGPIO[0] DA[26] DA[28] DA[29] DA[30] CSn[1] RVDD RVDD RVDD RVDD RTC_VDD ASDI2 DIOWn EGPIO[1] EGPIO[4] WRn DA[24] DA[25] **NC** CVDD RVDD RVDD ASDI DIORn EGPIO[3] EGPIO[6] EGPIO[7] SDCSn[1] SDCSn[2] SDCLKEN DTRn DA[27] RGND RGND RGND RGND RGND RGND ARSTn
Ball
L3 L4 L5 L8 L9 L10 L11 L12 L13 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M8 M9 M10 M11 M12 M13 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N6 N8 N9 N10 N11 N12 N13 N15 N16 N17 N18 N19 N20 P1 P2
Signal
RXCLK MDIO MDC RGND RGND RGND RGND RGND RGND **NC** ROW[4] ROW[5] ROW[6] ROW[7] CGND RXERR MIIRXD[0] MIIRXD[1] RXDVAL RGND RGND RGND RGND RGND RGND RXD[2] TXD[1] ROW[1] ROW[2] ROW[3] TXCLK MIITXD[3] MIITXD[2] CVDD TXERR RVDD RGND RGND RGND RGND RGND RGND RVDD SLA[1] RTSn RXD[1] TXD[2] ROW[0] MIITXD[1] MIITXD[0]
Ball
T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2
Signal
SCLK1 Yp **NC** DAC_GND USBp[1] ASDO CGND CVDD P[17] P[13] P[11] SPCLK P[7] IDECS0n CVDD VS1 MCBVD2 MCWRn TDI TEST[0] INT[1] SSPTX1 Xm sYp USBm[2] USBp[0] ASYNC RDLED P[12] XTALO HSYNC P[6] P[0] IDEDA[1] READY MCD2 MCDAENn IOWRn TCK TEST[1] EEDAT SSPRX1 Xp sXm ADC_VDD USBp[2] **NC** **NC** XTALI V_CSYNC
14
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
DS515PO3
EP9312 Preliminary Ball
C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8
Internet Audio Jukebox Processor Signal
TXEN BRIGHT P[16] RVDD RVDD USB_VDD SLA[0] INT[3] RXD[0] TXD[0] CRS CLD **NC** P[15] P[10] RVDD RVDD RVDD RVDD RVDD RVDD USBm[1] ABITCLK GRLED INT[2] CTSn DD[15] BLANK P[14] PLL_VDD PLL_GND P[8] P[2] VS2 MCADENn MCRDn **NC** TACK
Signal
AD[0] DA[21] DA[16] DA[12] DA[7] EGPIO[12] DA[5] WAITn RTC_GND RSTOn CSn[4] CSn[5] DD[14] AD[25] AD[22] DD[10] DD[5] CVDD AD[11] AD[7] DA[19] DA[18] DA[11] DA[6] EGPIO[13] DA[4] DD[1] RTCXTALO PRSTn IORDY DA[31] CGND CSn[2] CSn[3] DSRn RVDD RVDD DD[2]
Ball
H17 H18 H19 H20 J1 J2 J3 J4 J5 J8 J9 J10 J11 J12 J13 J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K8 K9 K10 K11 K12 K13 K16 K17 K18 K19 K20 L1 L2
Signal
EGPIO[5] EGPIO[8] EGPIO[9] CVDD DQMn[3] CASn RASn SDCSn[0] SDCLK RGND RGND RGND RGND RGND RGND EGPIO[2] COL[6] CGND COL[5] COL[4] DQMn[2] DQMn[0] SDWEn DQMn[1] SDCSn[3] RGND RGND RGND RGND RGND RGND COL[7] COL[2] COL[1] COL[3] COL[0] MIIRXD[2] MIIRXD[3]
Ball
P3 P4 P5 P6 P15 P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 R6 R7 R8 R13 R14 R15 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
Ball
W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
Signal
**NC** P[3] IDECS1n CGND MCWAITn MCBVD1 MCREGn IORDn MCRESETn TMS EECLK SFRM1 CGND sXp ADC_GND CDACO USBm[0] USB_GND P[9] P[5] P[4] P[1] IDEDA[0] IDEDA[2] MCD1 MCDIR MCEHn MCELn WP TDO TREQA INT[0] CVDD Ym sYm DAC_VDD USB_VDD USB_GND
DS515PO3
(c)Copyright 2001 Cirrus Logic (All Rights Reserved)
15

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